Satellite commutator having reed relay matrix



A. F. HOGREFE A 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX I5 Sheets-Sheet 1 FiledMay '7, 1963 ATTORNEY Nov. 15, 1966 A. F. HOGREFE 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX 5 Sheets-Sheet 2 Filed May7, 1963 RESET www ATTORNEY Nov. 15, 1966 A. F. HOGREFE 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX Filed May 7, 1963 5Sheets-Sheet 5 FROM GATE DRlvE AMPLIFlER RESET i I /04 Y @e /02l g 88.55' g i l f Pla: '84,@5i l 36 5" 56' hl I /03 jI 56 90' C?? i I 96' l l52 n l 94, F/ G 3 54' 37 66\ SE 70' /0\0 msg -//0 65\ k $721 6a 35, 57 l:To 65 /20 To MoNnomNe clRculT /20 To MoN|ToR|NG clRculT OUTPUT ARTHURF. HOGREFE INVENTOR.

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ATTORNEY United States Patent 3,286,234 SATELLITE COMMUTATOR HAVING REEDRELAY MATRIX Arthur F. Hogrefe, Silver Spring, Md., assignor to theUnited States of America as represented by the Secretary of the NavyFiled May 7,1963, Ser. No. 278,793

8Claims. (Cl. 340-166) This invention relates in general to timemultiplexing equipment and, more particularly, toan electro-mechanicalcommutator utilizing reed relays in its connection matrix. v

The present invention generally -rese-mbles commutating equipment whichis `well-known and has existed for many years. However, the instantinvention includes several additional unique features which render itsingularly suitable for application in satellite systems. Morespecifically, it employs reed relays for making successive connections,and controls the operation of these relays by reliable electroniccircuits, thereby combining the advantages of both electronic circuitsand mechanical devices. v

The instrumentration of the electronic circuits of the present inventionincl-udes safety features for eliminating any interaction betweensatellite monitoring systems, in the event of anycatastrophic.malfunction during launch affecting theinterconnection of-any twoor more channels of the commutator. Additionally, theinstantinvention is designe-d to operate on a 75% duty cycle, thereby reducingpower drain and, more importantly, facilitating the design of groundequipment which is used in conjunction thereto.

Another beneficial feature resulting from the employment of electroniccontrol .circuitry is the use of a series of connected flip-flops ascounters, which flip-flops have one of their stages connected to acommon inhibiting current source.V This current source acts .as a safetyfeature whereby only one flip-flop can be energized at a time incontradistinction to the use of a voltage level, which level allows theenergizing of more than one stage under noisy operating conditions. Such.a spurious operation persists indefinitely until reset by turn off ofthe ring counter, and causes the loss of information during that period.Also, the iiip-flop ring counters of the present invention have biasnetworks to prevent la complete circuit failure upon a momentary losso-f the single existing excited flipiiop due to noise. These networksautomatically cause the first stage of each of the counters to be turnedon and allow normal operation to begin again.

The mechanical advantages lent to the instant invention through the useof reed relays include complete isolation between the .separatesatellite systems which are gathering information, and a resultingabsence of cross talk between channels. Therefore, a commutator can bemade with any number of channels without any inherent limit.Additionally, the use of the reed relays permits the sensing of signals100 t-o 100() times smaller than is possible with the use of anelectronic connecting matrix.

One object of the present invention, therefore, resides in the provisionof a satellite commutator which is suited for yremote operatingconditions by the use of built-in safety features.

Another object of the invention is to provide a satellite commutatorwhich exhibits zero cross talk and provides suicient isolation betweeninput channels.

A further object of the invention is toprovide a satellite commutatorwhich is able to resolve very small input signals.

A still lfurther object of the invention is to provide a satellitecommutator which allows the employment of hi-gh accuracy groundequipment.

and drive' circuit.

Mice

yOther objects yand many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understoodV byreference to the following detailed description when considered inconnection with the accompanying drawings, wherein:

FIG. 1 is a generalized block diagram of the instant invention;

FIG. 2v is a schematic diagram of the current source, bias network Aandfirst counter stage -of the X-axis driver shown in FIG. l;

n FIG. 3 is a schematic diagram of the current source, bias network,first counter stage and positive amplifier employed in the Y-axisdriver;

FIG. 4 is -a schematic `diagram of the reed relay matrix employed in theinstant invention showing ho-w an individual relay is energized; `andFIG. 5 shows typical relay circuits employed in the instant invention.

Briefly, the instant invention comprises a reed relay matrix forconnecting the output of various electronic circuits dispersed withinthe satellite, which circuits monitor the functioning of the satelliteat selected points. The connecting matrix is driven Iby aplair ofcounters which sequentially energize the relays in the matrix, whichcounters in turn are synchronized and driven by a clock In operation,vthe clock and drive circuit may either free run or be synchronized to anexternal source of extreme timing accuracy. However, the embodimentshown is free running.

Referring to FIG. l, the clock and drive circuit 1,

employed in the instant invention has three output signalls, the firstof which is connected to an X-axis driver 2, which driver includes aplurality of counters 3, the second is connected to a Y-axis driver 4,which driver includes a plurality of counters 5, and the third isconnected to a plurality of positive amplifiers 7. The counters 3 areconsecutively connected together and form a one to six counter, whilethe counters 5 are conne'cted together and form a one to five counter.The outputs of the counters 3 directly drive the X-axis of a reed relaymatrix 9, while the outputs of the counters 5 are first connected to theamplifiers 7 for the proper polarity inversion before being applied tothe Y-axis of the matrix. Only one of the lines from each of thecounters 3 and 5 is energized at any time. A relay positioned in thematrix 9 and located at the intersection of the pair of energized linesis activated, thereby connecting one output of ya satellite monitoringcircuit to the satellite transmitting'equipment rfor transmission to theground.

For clarity in the relay matrix 9, shown schematically i in FIG. l andin greater detail in FIG. 4, the lines drawn horizontally willl bedesignated rows, whereas those arranged vertically will be calledcolumns The clock and drive circuit 1 contains features whereby it mayeither be free running or synchronized to an external source. A pair ofcascaded amplifiers 14 and 16 take un external repetitive synchronizingsignal when applied *o an input terminal 17 and apply it t-o an astabledip-flop 1'8, which flip-flop would also free run in the absence of theinput synchronizing signal. The fiip-flop 18 has two output signals, oneof which is applied to a divide by 2 tiip-fiop 20, and the other isapplied to a gated amplifier circuit 22. The flip-flop 20` produces anoutput signal at a rate one-'half its input signal, which output signalis also applied to the gated amplifier 22. The two input signals appliedto the input of the amplifier 22 are combined at its input in the formof a logical or gate operation so that the output signal has a dutyfactor of The output from the amplifier 22 is applied to a driveamplifier 24, which amplifier increases the power of its input signaland applies its output signal to a one-shot Hip-flop 26 and a gate driveamplilier 28. The one-shot flip-flop 26 develops the drivepulses foradvancing both the counters 3 and 5, while the drive amplifier 28produces the gating signal applied to the positive going amplitiers 7and produces the 75% duty factor for-the reed connecting matrix 9. Theip-flop 26 is connected to a current source 29 employed in both theX-axis and Y-axis drivers 2 and 4, which drivers additionally employbias networks 30 connnected to voltage source terminals 31 and to therst counter stages of each of the drivers.

One of the currentsources 29 for the counters 3 is shown schematicallyin FIG. 2, and includes a pair of transistors 32 and 33.v A base lead 34of the transistor 32 is connected to ground 35 by a series connectedresistor 36 and diode 37, which diode 37 is connected so as to maintaina slightly positive signal at its junction with the resistor 36.Additionally, the base lead 34 of the transistor 42 is connected to thesource of positive potential 31 by a series connected diode 38 andresistor 39, which source 31 may be a positive 22 volts, and which diode38 is connected s o as to allow a ilow of biasingl current from thesource 31 to ground 35 through the divider 39, 38, 36 and 37. Acapacitor 40 is connected in parallel with the series connected diode 38and resistor 39. An emitter lead 41 of the transistor 32` is connectedto the base lead 42 of the transistor 33 and aA collector lead' 43 of atransistor 3 2`is connected to a collector lead 44` of the transistor33. The emitter lead 41 of the transistor 32 is connected to the'potential source 31 by a resistor 45, and an emitter lead 46 of thetransistor 33 is connected to the potential source 31 by a pair ofparallel connected resistors 48 and 49. The values of the resistors 48and 49 are chosen to obtain a 16 volt level at' the emitter lead'46 ofthe transistor 33 when one ip-op only is conducting.

The biasingnetwork of the rst counter 3 is used to reset the firstcounter Whenever the one on stage of the X-'axis driver' is lost, andcomprises a pair of resistors 50 and 51,' a capacitor S2, and ,a diode53. The

resistors 50 and 51 are connected in series with an addi-iA tionalresistor 54 between the potential source 31 and ground 35. The capacitor52 is connected from lthe junction of the resistors 50 and 51 to ground`35, and the diode 53 connects a base lead 55 of a transistor 56 to thejunction of the resistors 50 and 51, and functions to pass negativesignals to said base of the transistor 56.

The remaining circuitry for the rst ip-iiop counter stage isidenticalfor the additional ve counter stages, which stages include, inaddition to the transistor 56, a' v second transistor 57, whichtransistor,"` has a diode 58 the matrix 9 by means of identical lines62. An emitter lead 65 of the transistor 57 is connected to the junctionof the resistor 36'and the diode 37 by a line 66, -and is also connectedto the emitter lead of the corresponding transistor in the next counterIstage by a line 68. A base lead 70 of the transistor 57 is connected toground 35 by a resistor 72, and to a collector lead 76 of the transistor56 byY a resistor 74. The input signal from the one-shot flip-flop 26 isapplied to the collector lead 44 of the transistor 33 by a line 78, andsaid collector lead 44 is connected to an emitter lead 79 of thetransistor 56 by a line 81 and to each succeeding emitter leads ofcorresponding transistors in the following counter stages by a line 82.A series connected diode 83 and to the base lead 55.

capacitor 84, a line 85 and a diode 86 connect the collector lead 76 ofthe transistor'56 to a base'lead 55 of the corresponding transistor, inthe following counter stage 3, and constitute the circuit over whichtrigger pulses pass to energize the subsequent counter ip-flop stage.The `diode 83 is connected to pass positive going signals from thecollector lead 76 to the base lead 55 and the diode 86 is connected topass negative signals A line 87 is connected between the junction of thediode 83 and the capacitor 84, and the junction of the resistors 51 and54.

A second biasing yarrangement for the iirst counter stage is thestandard biasing arrangement for the remaining stages -in'the X-axisdriver and comprises, in addition to the diode 86, -a pair of resistors88 and 90 and an additional diode 94. The resistor 88 is connectedbetween the potential source 31, and the base Ilead 55 of the transistor56. The diode 86" is connected in series with the resistor 90` and thediode 94 between the base lead 55 of the transistor 56 and the collectorlead `60 of the transistor 57. Both diodes are 4arranged to passnegative sig` nals from the collector leai 60 to the base lead 55. Aresistor 96 is connected between the junction of the resistor 90 randthe diode 94, and the junction of the capacitor continuous recycling.v'l

' FIGL 3 shows the positive amplifiers employed in the Y-axis driver,including considerable circuitry that is identical with that describedin FIG. 2. Therefore the gsame numbers raised to the prime are used toidentify components identical to tho-se used in FIG. 2. The col-y atransistor `104. An emitter lead 105 of the transistor 104 is connectedto the gate drive amplifier 28 by a series connected diode 106 and aline 107, and the collector lead 108 o-f the transistor 104 isconnect-ed to ground 35 by a resistor 109 and to the rst row of the reedrelay matrix 9 by :a line 110; Succeeding positive amplifiers tion. Eachcolumn of t-he matrix is energized by a separate line 62 or 62V from oneof the counter stages 3 contained -in the X-axis driver 2, and each rowis ener- Igized by a separate l-ine 110 or 110 from one of the counterstages 5 contained in the Y-axis driver 4. Since the drivers 2 and 4each employ a mutually prime number ot counters, which numbers have nocommon factor other than one, the relays are energized in ythe orderindicated in FIG. 4 by consecutive K numbers K1 through K30.

A typical re'lay energizing circuit 114, shown in FIG. 4, comprises adiode 115 in series with an individual relay coil 17, which elements 115and 117 are connected between `the lines k1105and 62, and a .diode 119connected across the relay Icoil 117 to provide damping. However,sometimes a icapacitor is substituted for the diode 119 to allow anoscillatory `damping and to prevent sticking of the matrix 9 by linesthe re1=ay contact arm 120 closes, the signal from one of the monitoringcircuits is transferred to t-he output terlm'inal 123 for transmissionover lthe satellite transmission system. The resistors 121 and 122reduce the signal amplitude for proper signal transfer within the systemrange. The value-s of these resistors 121 and 122 depend upon the typeof monitori-ng circuit to which it is connected but are easilydetermined yaccording to well-known design principles; however, theresistor 121 shoul-d be larger than 1000 ohms to prevent interaction ofseparate satellite monitoring systems, which interaction occurs Iuponthe simultaneous unintentional closure of two or more relay a-rmfs 120.

In operation, tihe free running flip-flop of the clock and drive circuit1 develops a series of pulses for use as the basic source of timingpulses thro-ughout the commutator. A-n additional logical or gatingcircuit 22 develops a drive waveform of about two seconds period with a75% symmetry, that is, `a wave-form which is at 'ground potential 25%'of the time and at a positive voltage potential t'h'e remaining 75 ofthe time. This output waveform simultaneously drives both the X-axis andthe Y- axis drivers 2 and 4. Since the first counter stage 3 and 5 ofeach axis driver is biased in such a manner as to assume the oncondition in the absence of any input signals, both counters willadvance sequentially from the first counter stage to the last stage,which stage then resets t-he first stage yto continue recycling. Atypical counter stage 3 .and 5 utilized in both .the X-axis and Y-axisdrivers 2 and 4 consists of the pair of transistors 56 and `57, as bestseen in FIG. 2. 'Ilhe transistors 56 and 57 are referenced from avoltage that is derived vfrom the current source 29, which source wiilsustain stable circuit conditions if, and -only if, a single counterstage is in the on condition. These counter stages are complementary,that is, both transistors are on at the same time. If the second counterstage shown in FIG. l, is off and `the first counter stage shownschematically in FIG. 2 is o-n, the following conditions are present:the capacitor 84 has a 15 vo'lt bias on the lead connected to the `diode83 and -a 20 volt bias on the lead connected to the diode 86. Thus,there is a potential of about five volts across this capacitor and ifthe rst counter stage is turned ofi the rinput side is pulled towardground by the resistor 54 and a resulting bias of 7 to 8 volts isapplied to the 'base lead 55 of the transistor S6', due to the divide-raction of the resistors 88 and 54. Such a voltage change occurs duringthe period when the output drive waveform from the one-shotmultivibrator 26 clamps the collectors 43 :and 44 of the transistors 32and 33 to ground. The capacitor 84 begins to charge and the bias issustained at the base lead 55 of the transistor 56',

wihichV bias causes the transistor 56 to turn on when the positiveperiod of the input waveform `from the one-shot multivibrator 26releases the current source, by enabling the second counter -stage t-oregenerate into the on state. The bases of the remaining transistors 55'are biased at 22 volts under the :same condition and have no tendency toturn on while the 'base lead 55 -of the transistor 56 is bia-sed at 17volts, a significantly greater potential than that allowed t-o turn thetransistor 56 back on again.

The first counter stage is always turned on if all the other counterstages are 'off, due to the special D.C. 'bias arrangement found only inthe first counter stage, which arrangement consist-s of the pair ofresistors 50 and 51, the capacitor S2 andthe diode 53. The positive turnon of the first counter stage occurs when the remaining stages are 'off,which condition allows the current source line 81 to rise almost to :thesupply voltage, therefore placing 22 volts .at the emitter 79 -of thetransistor 56.` Since the special bias arrangement places 18 volts onthe 'base llead 55 `of the transistor 56, itis biased on..

The transistor 57 provides the regenerative action necessary to placetlhe transistor '56 into full conduction, while the diode clamp 58,which is connected to the potentia'l source 31, is provided to protectthe collector 60 of the ltransistor 57 in the event of impropercommutator operation and large ki-ck voltage from the relay coils. Thediode 86' is used in the base lead 55 of the transistor 56 t-o preventthe turn on of the previous stage from placing excessive voltage acrossthe inter-nal base to collector junction of the transistor 56. The diode83 prevents the voltage across the coupling capacitor 84 from feedingback Iinto the base of the transistor 57 after it is turned off Theoperation of the Y-axis driver 4 is identical to that of the X-axi'sdriver 2 just described. However, each stage drives into a positiveamplifier 7, as seen in FIG. 3, by .the series connected line 100 andt-he resistor 101. The positive amplifier 7 Iobtains the negativevoltage from the colll-ector llead 60 of the transistor 57 and invertsit to a positive voltage signal Ihaving a magnitude of approXimately thevolt-age source at the connection of the line 110 with the resistor 109.

Therefore, a positive signal from the Iline 110 in FIG. 3 and a negativesignal from the line 61 in FIG. 2 are applied across the relay coil 117,as seen in FIG. 4, to energize the relay.

The instant invention is stable in operation, having a minimum of changein its timing waveforms. This stability, in addition to purposelygrounding two or three consecutive channels, allows positive framesynchronizing with supporting ground equipment.

Component values which have been selected for use in a preferredembodiment of the instant invention are as follows:

R36 ohms 121K R39 do 38.3K R45 do 17.8K R50, R72, R74, R do 31.6K R51 do68.1K R54 do 8.25K R74, R101 do 14.7K R88 do 46.4K R96 do 422K R102 d010K R109 do 56.2K C40, C52 /rf .01K C84 af .02K D37, D53, D58, D83, D86,D94, D106 IN 3070 D38 IN 3064 Q32, Q56 320S2 Q33, Q104 2N2303 Q57 2N1711Obviously, many modifications and variations of the present inventionare possible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay De practiced otherwise than as specifically described.

What is claimed is:

1. An electromechanical commutator circuit, prising,

a first flip-dop for developing basic timing signals,

a second flip-flop driven by said first flip-flop for dividing in halfthe frequency of the basic timing signals,

a gating amplifier connected to the output of both of said flip-flopsfor performing a logical or function in generating a waveform having apartial duty cycle,

a one-shot flip-flop electrically connected to said gating amplifier fordeveloping drive pulses,

a drive amplifier electrically connected to said gating amplifier forfurnishing gating pulses,

an X-axis driver actuated by said one-shot flip-flop for sequentiallydeveloping a plurality of energizing voltages,

a Y-axis driver actuated by said one-shot dip-flop and controlled bysaid drive amplifier for sequentially developing a second plurality ofenergizing voltages, and

COIII- a plurality of reed relays formed as a matrix and connected tosaid X-axis driver and to said Y-axis driver, whereby said pair ofenergizing voltages is consecutively applied to each of said relays foractivation thereof.

2. A commutator circuit as recited in claim 1, wherein said X-axisdriver comprises,

a plurality of flip-flops connected to form a recirculating counter,

a current source connected to each of said fiip-flops for individuallyfurnishing an energizing voltage to each of said flip-flops,

means for initially biasing the first of said flip-fiops to conduction,and

means connected between consecutive flip-flop stages for sequentiallyenergizing the remaining plurality of fiipflops.

3. A commutator circuit as recited in claim 1, wherein said Y-axisdriver comprises,

4. An electromechanical commutator circuit, compris` lng,

a first flip-Hop for developing basic timing signals, a second flip-flopdriven by said first flip-flop for dividing in half the frequency of thebasic timing signals, a gating amplifier connected to the output of bothof said fiip-fiops for performing a logical or function by generating awaveform having a 75% duty cycle, one-shot flip-flop electricallyconnected to said gating amplifier for developing drive pulses,

a drive amplifier electrically Aconnectedto said gating amplifier forfurnishing gating pulses,

a first plurality of flip-flops connected to form a first recirculatingcounter for generating an energizing voltage,

a second plurality of fiipffiops connected to form a secondrecirculating counter,

currentsources operated by said owne-shot-fiip-op and connected to eachof said pluralityrof fiip-fiops for individually furnishing anenergizing voltage to each of said flip-flops, means for initiallybiasing the first of said flip-fiops in said first and said secondcounters to conduction, means connected between consecutive fiip-flopstages in said first and said second counters for sequentiallyenergizing the remaining pluralityl of flip-flops in each of saidcounters,

a positive amplifier connected to each of said flip-flops' in saidsecond counter and controlled by said drive amplifier for generating asecond energizing voltage, and

a plurality of reed relays formed as a matriX and connected to saidfirst counter and to said positive arnplifiers, whereby each of saidrelays is consecutively activated by said pair of energizing voltages.

5. A commutator circuit as recited in claim 4, wherein said currentsource comprises,

a rst transistor having a base, an emitter and a collector,

the collector of said first transistor being electrically connected tosaid one-shot fiip-flop and to each of said fiip-fiops in its respectivecounter,

l a second transistor having an emitter, a base and a collector, thecollector of said second transistor being connected to the collector ofsaid first transistor, means for biasing said first transistor toconduction in the presence of a positive potential signal from saidVone-shot flip-flop, the emitter of said first transistor being connectedto the base of said second transistor for causing said second transistorto conduct at the same time the first transistor conducts, and meansconnected to the emitter of both of said transistors for regulating theflow of current through said transistors, whereby a stable current levelis set at the emitters of said transistors, which level is capable ofcausing only one of the counter stages to be placed in conduction. 6. Acommutator circuit as recited in claim 4, wherein one of said counterflip-flops comprises,

a first PNP transistor having a base, an emitter and a collector,

the emitter of said first transistor being connected to connected to thebase of said second transistor and to ground,

the emitter of said second transistor being connected to a firstpositive potential,

means for connecting the collector of said second transistor to a secondpositive voltage potential greater than said first positive potential,

means for connecting the collector of said second transistor to the baseof said first transistor and to the second source of positive potential,and

means for biasing said first transistor to conduction upon operation ofsaid sequential energizing means in transferring a triggering pulse fromthe first transistor of a prior counter flip-flop.

7. A commutator circuit as recited in claim 4, wherein said sequentialenergizing means comprises,

a capacitor electrically connected to said collector of said firsttransistor for charging during the period of conduction of the firstcounter flip-fiop and for discharging during the grounding of saidcurrent source to create a trigger pulse for application to said base ofsaid subsequent counter Hip-flop,

a first diode electrically interposed between said capacitor and thecollector of said first transistor on said first counter flip-Hop forpreventing the voltage across said capacitor from feeding back into thecollector of the first transistor and that had just been on, and

a second diode interposed between said capacitor and the base of thefirst transistor of said subsequent counter flip-fiop for preventing theturn on of said first counter flip-flop from placing excessive voltageacross the base to collector junction of said subsequent counterflip-flop.

8. A commutator circuit as recited in claim 6, wherein said collectorconnecting means of said second transistor further includes, v

a diode clamp electrically interposed between the collector of saidsecond transistor and said second potential source for protecting saidsecond transistor from large voltage surges caused by impropercommutator operation.

No references cited.

NEIL C. READ, Primary Examiner.

H. PITTS, Assistant Examiner.

1. AN ELECTROMECHANICAL COMMUTATOR CIRCUIT, COMPRISING, A FIRSTFLIP-FLOP FOR DEVELOPING BASIC TIMING SIGNALS A SECOND FLIP-FLOP DRIVENBY SAID FIRST FLIP-FLOP FOR DIVIDING IN HALF THE FREQUENCY OF THE BASICTIMING SIGNALS, A GATING AMPLIFIER CONNECTED TO THE OUTPUT OF BOTH OFSAID FLIP-FLOPS FOR PERFORMING A LOGICAL "OR" FUNCTION IN GENERATING AWAVEFORM HAVING A PARTIAL DUTY CYCLE, A ONE-SHOT FLIP-FLOP ELECTRICALLYCONNECTED TO SAID GATING AMPLIFIER FOR DEVELOPING DRIVE PULSES, A DRIVEAMPLIFIER ELECTRICALLY CONNECTED TO SAID GATING AMPLIFIER FOR FURNISHINGGATING PULSES, AN X-AXIS DRIVER ACTUATED BY SAID ONE-SHOT FLIP-FLOP FORSEQUENTIALLY DEVELOPING A PLURALITY OF ENERGIZING VOLTAGES, A Y-AXISDRIVER ACTUATED BY SAID ONE-SHOT FLIP-FLOP AND CONTROLLED BY SAID DRIVEAMPLIFIER FOR SEQUENTIALLY DEVELOPING A SECOND PLURALITY OF ENERGIZINGVOLTAGES, AND A PLURALITY OF REEDS RELAYS FORMED AS A MATRIX AND CON-